Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. The desire for higher performance circuits has driven the development of high-speed sub-100 nanometer (nm) silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) technology. In SOI technology, metal-oxide semiconductor field-effect transistors (MOSFETs) are formed on a thin layer of silicon overlying a layer of insulating material such as silicon oxide. Devices formed on SOI offer many advantages over their bulk counterparts, including reduced junction capacitance, absence of reverse body effect, soft-error immunity, full dielectric isolation, and absence of latch-up. SOI technology therefore enables higher speed performance, higher packing density, and reduced power consumption.
There are two types of conventional SOI devices: partially-depleted SOI (PD-SOI) devices, and fully-depleted (FD-SOI) devices. A conventional PD-SOI transistor device is one in which the silicon body thickness is thicker than the maximum depletion layer width in the silicon during device operation, and a conventional FD-SOI transistor device is one in which the body thickness is thinner than the maximum depletion layer width in the silicon during device operation. Consequently, during operation, the PD-SOI device experiences a “partial” depletion of the silicon body, while the FD-SOI experiences a “full” depletion thereof. The conventional PD-SOI and FD-SOI devices are planar devices and thus are formed in the plane of the wafer.
Each of the PD-SOI and FD-SOI devices have their own respective advantages. For example, while PD-SOI devices have the merit of being highly manufacturable, significant design burdens are experienced due to floating body effects associated therewith. In PD-SOI devices, charge carriers generated by impact ionization near one source/drain region may accumulate near the other source/drain region of the transistor. When sufficient carriers accumulate in the floating body, which is formed right below the channel region, the body potential is effectively altered.
Floating body effects occur in PD-SOI devices because of charge build-up in the floating body region. Such floating body effects can result in kinks in the device current-voltage (I–V) curves, thereby degrading the electrical performance of the circuit. In general, the body potential of a PD-SOI device may vary during static, dynamic, or transient device operation, and is a function of many factors like temperature, voltage, circuit topology, and switching history. Therefore, circuit design using PD-SOI devices must take such factors into account, and accordingly there are certain circuit applications where the floating body effects represent a significant barrier for the adoption of PD-SOI technology.
Another way of avoiding floating body effects in SOI devices is to adopt a fully-depleted SOI (FD-SOI) technology. FD-SOI devices do not suffer from floating-body effects due to the fact that the body is fully-depleted during device operation. FD-SOI technology is therefore relatively design-friendly with respect to floating-body effects. FD-SOI devices are also believed to provide better junction capacitance, lower off-state leakage, fewer soft errors, lower operating voltages and lower gate delay than PD-SOI devices.
Traditionally, in a FD-SOI technology, devices with a low body-doping and/or a thin body thickness are used. Additionally, for good control of short-channel effects, the device body thickness is usually reduced to less than one third of the gate length. SOI substrates with uniform ultra-thin Si films, as required for the manufacture of FD-SOI devices with ultra-thin body, however, are difficult to obtain or fabricate and non-uniformities in the Si film thickness may result in significant fluctuations in the device characteristics and negatively impact the ease of manufacture. In addition, it is difficult to build analog transistors, high voltage I/O transistors, or transistors with different Vt's on the same chip as high performance FD-SOI transistors. These types of transistors are more readily built with PD-SOI.
Consequently, there is a need for a method to form both PD-SOI and FD-SOI devices reliably in a single fabrication process, wherein either device can be employed based on circuit application requirements.